Z
ziadost
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- #41
same here... australian channel frequencies can be found at http://www.dba.org.au
not sure about UK though...
not sure about UK though...
ziadost said:does anything at all work without the original avermedia drivers?
feel_hobart said:Does that mean we could manually tune if we know our channel frequencies. because i would be happy with that
dman_lfc said:feel_hobart said:Does that mean we could manually tune if we know our channel frequencies. because i would be happy with that
No I tried that also.
DMAN
dman_lfc said:
dman_lfc said:Interesting...
....
You'll notice the PLL is 0x61 vs 0x60 on the Fusion Lite card which is the closest match to the AverMedia 771 since the bridge chip is the same as well as the demodulator.
The I2C address is also C2 vs C0 on the Fusion Lite tuner.
What seems to be evident is that the DVICO driver is using hard-coded I2C address for PLL chip equal to hC0, which is the main reason why the driver cannot tune !
I am not sure if this will be enought, there are two bytes of configuration for a PLL chip and those have to be checked with the data comming out from Aver driver (as I have not datasheet for a tinbox and some of the PLL parameters depend on the PCB layout, etc.) and finally there is the problem with data transfer mode (serial vs. parallel), but if the PLL will opereate the mt352 have to lock on the channel and this will be indicated by the driver. I have spent three hours now looking at the DVICO's code, I expect that "our" part will be in the zulutune.sys, I have found something, which seems to be an initialisation according the registry, but there is no C0 anywhere there , which corresponds to my assumption that it is hardcoded somewhere else in the driver. There is one more problem I have found yesterday, I have used ScanChannelsBDA.exe for a test and I have entered 506000kHz as a frequency and 8Mbps as a bandwidth, but in the sequence I have captured were data for a 7M bandwidth, but I am not sure it this is not a problem within the ScanChannelsBDA.exe itself or not. What was great, the PLL divider seems to correspond to a desired frequency 506MHz (minus the 36.167MHz IF) which is correct !dman_lfc said:What seems to be evident is that the DVICO driver is using hard-coded I2C address for PLL chip equal to hC0, which is the main reason why the driver cannot tune !
So if we force the driver to use C2 we may get somewhere...
DMAN